Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...

As most ASIC designers are aware, there are two primary test-related issues that cause a high degree of pain and schedule delay in creating ASIC designs — the difficulty in adhering to DFT (Design For ...

Magma Blast Create SA, Blast Fusion SA and ChipX CX6000 Structured ASIC combine to reduce cost and cycle time of high-performance designs SANTA CLARA, Calif., Nov. 9, 2005 - ChipX, the structured ASIC ...