Adarsh Mittal, a senior application-specific integrated circuit engineer, explores why many memory performance optimizations ...

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver ...

Designing a memory subsystem is complex and can be a significant part of a system design and directly impact time to market. Design and development complexity is increased when both volatile and ...

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...