To overcome 45-nm process challenges, semiconductor intellectual property (IP) providers and foundries are collaborating to provide designers with a combination of design resources and manufacturing ...

DesignWare Interface IP for the most widely used protocols delivers the required high bandwidth and low latency for efficient data connectivity in compute-intensive designs on TSMC N4P process ...

The industry’s response is to split compute, memory, and I/O across dies, XPU chiplets are pushing toward the reticle limit, and stitch it all together with high‑bandwidth, energy‑efficient die‑to‑die ...

Deciding what to patent can be a confusing process but by creating a formal process it is something that every startup can manage. Intellectual property (IP) is one of the most valuable assets of a ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Uniquify, a leading high-end System-On-Chip (SoC) fabless manufacturer and DDR memory IP provider, today announced the availability of a new LPDDR4 Super Combo IP ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the immediate availability of a complete, silicon-proven Cadence ® IP supporting the DDR5 and LPDDR5 DRAM ...

The complexity of integrated circuit (IC) design has expanded a billion-fold since the invention of the first transistor, guided by the famous “Moore’s Law” of the semiconductor world. An important ...

Multi-standard memory interface IP allows a wide range of memory devices targeting high-capacity, high-speed, low-power and low-cost applications SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design ...

Creating reusable and portable analog intellectual property (IP) is a key trend to watch in EDA for 2009 and beyond. Finding a way to develop reusable analog IP will allow designers to build ...