EDN

Standard socket interface tapped

Emerging 2.5G/3G wireless markets are introducing new data types and application performance requirements into the handheld-terminal market. But the market promises to be so dynamic that a new level ...
Embedded

Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...
Design-Reuse

Standard Debug Interface Socket Requirements For OCP-Compliant SoC

Gilbert Laurenti, Texas Instruments Inc. Abstract Debug for SoC adds new requirements and challenges in terms of adding visibility and control to a system, simplifying integration of hardware and ...
Electronic Design

Group Forms To Support Standardized IP Core Socket Interface

For system-on-a-chip (SoC) design to become mainstream, it be-hooves the semiconductor in- dustry to embrace a common intellectual property (IP) core interface that would make IP integration a true ...
Design-Reuse

Standard socket interface tapped

Emerging 2.5G/3G wireless markets are introducing new data types and application performance requirements into the handheld-terminal market. But the market promises to be so dynamic that a new level ...