EDN

IC static timing tool aids predictability

NanoTime is a next-generation transistor-level static timing analysis solution that provides concurrent timing and signal integrity analysis for ASIC designs. Its performance and capacity allow ...
EDN

Statistical static timing analysis tool startup closes first funding round

To support the growing demand for statistical static timing analysis (SSTA) tools in the design and verification of highly-complex SoCs, Santa Clara, Calif.-based startup Altos Design Automation Inc.
Electronic Design

Static Timing Analyzer Goes Multicore And Distributed

They said it couldn't be done, but Synopsys has imbued its PrimeTime 2009.12 static timing analyzer with the ability to run in multi-threaded and distributed multicore modes. Synopsys continues to ...
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...
Business Wire

Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus ™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity ...
Semiconductor Engineering

What Happened To Statistical Static Timing Analysis?

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).