The goal of this project is to build a 32-bit 5-stage pipelined MIPS-based RISC core based on Harvard Architecture. MIPS ISA (Instruction Set Architecture) was used to develop the MIPS processor, ...

I was looking around at opencores.org and found the mpx project. I didnt realize it was a mips processor. I had tried the m1_core project which I dont think anywhere describes itself as being a mips1 ...