IEEE

Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design

Abstract: This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be ...
IEEE

Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip ...

Abstract: 3-D Network-on-Chip (NoC) technology has emerged as a compelling solution in modern System-on-Chip (SoC) designs. This NoC technology effectively addresses the escalating need for ...