A SystemVerilog implementation of an IEEE 754 double-precision floating point subtractor, verified at RTL level and pushed through full ASIC physical design using the OpenLane flow on the sky130 PDK.

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Abstract: In this paper, we propose three modular multiplication algorithms that use only the IEEE 754 binary floating-point operations. Several previous studies have used floating-point operations to ...

The Top 500 list of supercomputers has come and gone again, and vendors have engaged in their usual round of self-congratulations and performance posting. All the talk of FLOPs can get a little ...

Do you remember the early days of social media? The promise of connection, of democratic empowerment, of barriers crumbling and gates opening? In those heady days, the co-founder of Twitter said that ...

Abstract: Published in "IEEE Transactions on Emerging Topics in Computing, Volume: 9, Issue: 3, JulySeptember 2021" and orally presented at ARITH 2021. Published in: 2021 IEEE 28th Symposium on ...